As an interconnection interconnecting between an impurity diffused region formed in a semiconductor substrate and a lead-out line from the impurity region, a local interconnection formed of a conductive layer below the first metal interconnection layer is often used. As a method of forming the local interconnection is known the method of forming a trench in an inter-layer insulating film covering a gate electrode down to the impurity diffused region and filling an interconnection material in the trench.
The followings are examples of related: Japanese Laid-open Patent Publication No. 08-330314; Japanese Laid-open Patent Publication No. 11-345887; and Japanese Laid-open Patent Publication No. 2000-114481.
However, in the above-described method of forming the local interconnection, photolithography is used in forming the trench in the inter-layer insulating film. In the photolithography, alignment is made by using the alignment mark of the base pattern (an active layer and/or a gate layer), which often causes the disalignment with a gate electrode. In forming a contact to be connected to the gate electrode, it is necessary to take into consideration the disalignment between the gate electrode and the local interconnection. For this, the allowable range of the disalignment of the contact must be set wide, which has been a factor for blocking the integration.